ASIC Engineering Technical Leader | Design Verification | Verilog, System Verilog, UVM, Testbench | Exp- 12+ Years
Cisco · Bangalore, India · 4mo ago
Meet the Team
Come join us and be part of the Cisco SiliconOne team and take part in crafting Cisco's groundbreaking Enterprise and Service Provider solutions by crafting some of the most complex chips being developed in the industry with the opportunity to get full exposure to all aspects of the systems and applications we build (Silicon, Hardware, Software, telemetry, security, etc). Our group offers a rare combination of a startup culture with the benefits of working for the top tier networking company in the world!
Your Impact
Cisco SiliconOne team is looking for an expert and talented ASIC Engineering Technical Leader. You will have an ASIC design verification background with hands-on experience in System Verilog and UVM methodology with in-depth knowledge of C++, scripting as well as ASIC/SoC development cycle, the best industry practices, from specification through tape-out and lab validation, and a proven track record of success in high-performance/high-volume products.
Collaborate closely with the design team and the hardware team to verify the ASIC in simulation, in emulation and during ASIC bring up.
Defining and Building UVM/System Verilog testbenches from scratch or enhancing existing testbenches with focus on reuse
Defining new DV methodologies or enhancing the existing methodologies
In-depth understanding of the architecture, and identification of problems and solutions.
End-to-end verification of one or more design blocks simultaneously while helping full chip team with integration and support.
Test plan generation, review, planning and execution, meeting all criteria of ASIC group.
Help in developing Emulation infrastructure using C/C++, that has to work with UVM based verification environment.
Gate level simulation and SDF back annotation for blocks as part of pre-silicon verification.
Code and Functional coverage-based simulation run, coverage collection, merging and working with designers to fill coverage holes.
Participating in all phases during ASIC development – RTL Verification, Emulation and post-silicon validation
Recommending best practice, identifying and suggesting innovative solutions to improve efficiency and quality
Leading and mentoring team of junior engineers in addition to the assigned task.
Strong focus on efficiency, quality, reusability.
Drives design verification solutions across the business. Ensure culture of code reviews and postmortems.
Act as the design verification lead, owning and leading all the above aspects, including driving the technical decisions made at the program level with rest of the dv teams, conducting weekly dv meetings, sync-ups with stake holders and cross functional teams like Architecture, Design, Emulation, SW, PSV.
Minimum Qualifications
BS/MS and 12+/10+ years respectively of hands-on experience in large-scale, high-performance ASIC design verification.
Hands-on and deep understanding of System Verilog and UVM methodology
Must have prior experience of developing UVM based infrastructure from scratch in more than one projects.
Ability to handle complex features/parts of chip independently.
Quick learner must be able to work in a fast pace dynamic environment and must be able to deliver quality even in aggressive schedule.
Strong teamwork quality – must be able to work in a highly collaborative team.
Overseeing reusability, comes up reusable solution to improve efficiency. Must always focus on efficiency and quality.
Ability to build, lead and mentor a team of engineers and ensuring quality delivery as a team.
Proficient in merging and analyzing code coverage data generated functional simulation
Good working knowledge in C, C++ programming and debugging skills
Experienced in system debug and SW/HW bring-up, system validation of silicon towards FCS.
Hardware Emulation Platforms and tools (such as EVE, Veloce)
Good written/verbal interpersonal skills and leadership skills.
Preferred Qualifications
Worked in DV methodology and definition of high-scale, high-performance ASICs.
Planning overall DV architecture strategy and defining the requirements.
Conducting & leading various test plan reviews.
Driving complex debugs and system level integration aspects
Valid experience in flow automation (scripting, Makefiles, etc), and establishing guidelines for the team.
Mentoring the senior resources in the team on DV and DV methodologies.
Good interpersonal skills, and validated leadership to accurately describe issues/improvements and lead team for on-time completion.
Excellent communication skills both verbal and written
Why Cisco?
At Cisco, we’re revolutionizing how data and infrastructure connect and protect organizations in the AI era – and beyond. We’ve been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital footprint.
Fueled by the depth and breadth of our technology, we experiment and create meaningful solutions. Add to that our worldwide network of doers and experts, and you’ll see that the opportunities to grow and build are limitless. We work as a team, collaborating with empathy to make really big things happen on a global scale. Because our solutions are everywhere, our impact is everywhere.
We are Cisco, and our power starts with you.