ASIC Synthesis and STA Engineer - New Grad

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. This role offers the opportunity to shape the front-end implementation of industry leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high-performance optical networking. 

How you will make an impact:

• Execute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation

• Develop and maintain timing constraints to support synthesis and signoff for subsystem integration

• Perform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout preand postlayout stages

• Validate clock domain crossings for toplevel ASIC integration to ensure functional integrity

• Create and optimize scripts, tools, and documentation that improve synthesis and static timing workflows

• Implement engineering change orders (ECOs) to support iterative design refinement

• Collaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities

The must haves:

• B.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)

• Knowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation

• Familiarity with RTL design principles and hardware description languages

• Ability to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules

Nice to haves:

• Experience with additional frontend or backend design activities such asfloorplanning, Design for Testability (DFT), or place and route

• Industry experience using synthesis and/or static timing analysis tools within an ASIC development environment

• Handson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies

• Scripting experience (e.g., Python,Tcl, or similar) to enhance automation and debug workflows

• Background supporting DSPcentric or highspeed ASIC development programs

• Experience working with external EDA vendors or foundry technology teams

Pay Range:

The annual salary range for this position is $70,700 - $112,900