Digital Design Verification Engineer
Broadcom · San Jose, United States +1 · 12d ago
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Job Description:
The ideal candidate has a proven track record of working on setting up testbenches for Design Verification using UVM on large designs.
Responsibilities include:
Operate with a high degree of autonomy, taking designs from initial specification through to timing closure and physical design hand-off
Collaborate cross-functionally with Architecture, Verification, and Physical Design teams to mitigate risks and ensure project milestones are met on schedule
High proficiency in UVM
Experience:
BSEE required, MSEE/PHD preferred
5+ years of industry experience with a focus on SoC integration, UVM test bench setup and design debug.
Compensation and Benefits
The annual base salary range for this position is USD 101,000.00 To USD 162,000.00
As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.
Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.
Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.
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