Principal Design Engineer (Virtual Solution)
Cadence · Shanghai, China · 3mo ago
Staff / Lead / PrincipalOn-siteSoftware Engineering
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Key Responsibilities
- Design and develop system-level AVIP solutions for emulation/prototyping platforms (Palladium, Protium)
- Build and integrate Accelerated Verification IP environments for complex SoC and subsystem validation
- Develop end-to-end verification flows including:
- AVIP integration
- Testbench and system modeling
- Bare-metal / driver-level validation
- Architect scalable solutions for multi-protocol system validation across multiple clock domains
- Optimize solutions for performance, scalability, and emulation efficiency
- Develop custom test cases, tools, and automation to enable advanced use models (embedded / co-emulation / hybrid flows)
- Work closely with cross-functional teams (PE, AE, customers) to debug and resolve system-level issues
- Contribute to next-generation AVIP methodology evolution, including integration with AI/ML-based verification flows
- Support customer enablement, including bring-up, debug, and solution deployment
Required Qualifications
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field with 5-10 years’ experience
- Strong expertise in high-speed protocols such as:
- PCIe, CXL, AMBA, UCIe, Ethernet (at least one)
- Strong RTL design experience (SystemVerilog / Verilog)
- Strong C/C++ development experience for modeling, testbench, or system integration
- Solid understanding of:
- System-level verification methodologies
- Emulation / acceleration flows
- Hands-on experience with Palladium / Protium / FPGA / emulation platforms is strongly preferred
- Good debugging skills for complex system integration issues
Preferred Qualifications
- Experience developing or using AVIP (Accelerated VIP) solutions
- Experience with end-to-end system validation flows (simulation → emulation → prototyping)
- Knowledge of UVM and verification frameworks
- Knowledge of Qemu/Gem5 or other system emulation projects
- Experience with multi-language environments (SV + C/C++ + Python)
- Familiarity with Emulation/Prototyping flows
- Exposure to AI/ML techniques applied to verification or tooling
- Strong problem-solving skills and ability to work independently
Soft Skills
- Excellent English communication skills (both verbal and written) are required
- Strong learning capability and adaptability to new technologies
- Ability to collaborate across global teams
- Proactive mindset in problem solving and customer engagement