Testsite Automation Layout Designer

Introduction

Youwillplay a critical role in enabling next-generation RF, analog, and mixed-signal technologies through the development and implementation of advanced test-site layouts. This position is responsible for leading the end-to-end execution of technology development test chips, from device-level test structures through tapeout and mask ordering, ensuring successful validation of new process technologies and delivery of high-quality PDK collateral.

The successful candidate will serve as a key interface between device engineering, process integration, circuit design, and layout implementation, translating technology requirements into manufacturable, high-performance layouts that meet stringent performance, yield, reliability, and quality objectives.

Key Responsibilities

• Lead the end-to-end layout implementation of technology development test chips, including device test structures, circuit test vehicles, tapeout, and mask order execution.

• DevelopcustomPCells,layout automation solutions using Cadence SKILL scripting to improve design productivity and quality

• Develop innovative RF, analog, and mixed-signal layout solutions that support technology development, characterization, and qualification activities.

• Collaborate closely with device, process, and modeling teams to define, validate, and optimize design rules, layout methodologies, and technology enablement strategies.

• Support new technology stack enablement through creation and validation of test structures, layout guidelines, and best practices.

• Drive continuous improvement of PDK quality, design rules, layout productivity, and design automation capabilities.

• Evaluate and resolve complex layout, manufacturability, reliability, and yield challenges during technology development and productization phases.

• Partner with cross-functional engineering teams to accelerate technology introduction, qualification, and production ramp while ensuring adherence to project schedules and quality targets.

• Contribute to the development of layout methodologies and automation solutions that improve efficiency and consistency across technology platforms.

• Provide technical leadership and mentorship to junior engineers and layout designers.

Leadership & Collaboration

• Act as a technical leader within multidisciplinary project teams, influencing technology decisions and driving execution across organizational boundaries.

• Lead small project teams and coordinate activities among design, process, device, modeling, and CAD/PDK development groups when required.

• Foster strong partnerships across global organizations to ensure rapid technology deployment and successful achievement of business objectives.

• Demonstrate strong communication, project management, and stakeholder engagement skills while driving initiatives from concept through implementation.

Required Qualifications

• Min 10years ofexperience in layout design, Layout automation and semiconductor technology development.

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.

• Strong software development skills withexpert level proficiency inCadence SKILLprogramming. Proven experience developing complex layout automation frameworks, custom PCells, and productivity-enhancing design tools.(mandatory)

• Hands-on experiencewith Cadence Virtuoso, customlayoutdesign, PCell development,layoutverificationmethodologiesandautomationframework developmentfor semiconductor testsite.

• Goodunderstanding of semiconductor process technologies, design rules, manufacturability, reliability, and yield considerations.

• Experience with test-chip development,DRC/LVSclosure,tapeout execution, and mask release processes.

• Familiarity with PDK development, design automation, and technology enablement methodologies.

• Proven ability to lead technical initiatives, collaborate across functions, and drive projects to successful completion

• Strong sense of ownership, urgency, and commitment to meeting project milestoneswhile maintaining high-quality deliverables.