Principal ASIC Verification Engineer
Hewlett Packard Enterprise · Sunnyvale, United States · 1mo ago
Who We Are:
Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good. If you are looking to stretch and grow your career our culture will embrace you. Open up opportunities with HPE.
Job Description:
This is a Hybrid role based in Sunnyvale, CA with an expectation that you’ll be in the office 2 days per week.
HPE Networking is a leading provider of advanced routers and switches for the internet. We keep the world connected with speed, reliability, security, and ease of use. At HPE Networking Silicon group, we push the boundaries of what is possible in a piece of silicon die. We build cutting edge networking chips used to build our world-class routers and switches.
Bring your passion and there are no boundaries to what you can accomplish here. We are like a start-up in a big company. Year after year, our group builds the most powerful and highest density networking chips.
As part of our fast-paced silicon group, you will become an expert in building high-speed ASICs, from specifications to final netlist. We give you opportunities to work on complex modules and subsystems where you can challenge yourself and grow.
Open communications, empowerment, innovation, teamwork, and customer success are the foundations of team culture. Thus, you set your own limits for learning, achievements, and rewards.
Position Summary
We are seeking a highly motivated Senior ASIC Verification Engineer to join our networking silicon development team.
Key Responsibilities:
Own and drive block-level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
Perform constraint-driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
Analyze simulation results using industry-leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
Collaborate with cross-functional teams to identify and resolve issues, ensuring high-quality ASIC/SoC deliverables.
Required Skills and Qualifications:
15+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
Hands-on experience in test planning, coverage analysis, and debugging of complex SoC designs.
Proficiency with industry-standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.
Preferred Skills and Experience:
Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
Familiarity with high-speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
Exposure to emulation environments, hardware acceleration, or traffic-model integration.
Knowledge of coverage analytics, regression dashboards, and continuous-integration flows (e.g., Jenkins).
Understanding of low-power (UPF) or formal verification methodologies.
Own and drive block-level/subsystem/FullChip verification efforts, from creating test plans to achieving comprehensive coverage closure
Experience with post-silicon bring-up and debug is a plus.
Familiarity with emulation environments and debug flows is desirable.
What We Can Offer You:
Health & Wellbeing
We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing.
Personal & Professional Development
We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division.
Unconditional Inclusion
We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good.
Let's Stay Connected:
Follow @HPECareers on Instagram to see the latest on people, culture and tech at HPE.
Job:
EngineeringJob Level:
TCP_05"The expected salary/wage range for this position is provided below. Actual offer may vary from this range based upon geographic location, work experience, education/training, and/or skill level.– United States of America: Annual Salary USD 174,000 - 352,500 in California
The listed salary range reflects base salary. Variable incentives may also be offered."
Information about employee benefits offered in the US can be found at https://myhperewards.com/main/new-hire-enrollment.html
HPE is an Equal Employment Opportunity/ Veterans/Disabled/LGBT employer. We do not discriminate on the basis of race, gender, or any other protected category, and all decisions we make are made on the basis of qualifications, merit, and business need. Our goal is to be one global team that is representative of our customers, in an inclusive environment where we can continue to innovate and grow together. Please click here: Equal Employment Opportunity.
Hewlett Packard Enterprise is EEO Protected Veteran/ Individual with Disabilities.
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