Principal Analog/Mixed Signal CAD Engineer

About Marvell

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. 

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. 

Your Team, Your Impact

We are seeking a Principal Analog/Mixed-Signal CAD Engineer to join our Central Engineering organization in Santa Clara, CA. In this role, you will help shape the next generation of design automation infrastructure that supports cutting-edge analog, mixed-signal, and silicon photonics IC development across the company.

This is a highly visible technical leadership role where your work will directly impact how Marvell’s global design teams build industry-leading semiconductor products.

You will join Marvell’s Central Engineering CAD team, a group responsible for building and supporting the advanced design infrastructure used by hundreds of engineers developing some of the industry’s most sophisticated silicon.
The team works at the intersection of EDA tools, semiconductor process technology, and circuit design, partnering closely with:
• Analog and mixed-signal IC design teams
• Silicon photonics engineers
• Foundry partners
• EDA vendors
• Device modeling and TCAD specialists

This collaborative environment gives you a unique opportunity to influence the design methodology and automation frameworks used across the entire company.

What You Can Expect

As a Principal Analog/Mixed-Signal CAD Engineer, you will play a critical role in developing and evolving the automated design flows that enable Marvell’s most advanced silicon programs.

Your work will directly improve engineering productivity, simulation accuracy, and design reliability across high-speed analog, RF, and photonics projects built on leading-edge process nodes.

Key responsibilities include:

• Architect, deploy, and maintain analog/mixed-signal simulation environments for advanced CMOS FinFET and BiCMOS technologies.
• Develop and support next-generation automated AMS design flows used across Marvell design teams.
• Partner with analog designers and EDA vendors to troubleshoot and resolve complex simulation and design flow challenges.
• Collaborate with foundry and TCAD teams on device modeling, simulation accuracy, and circuit behavior.
• Evaluate and benchmark new EDA tools and methodologies to improve design productivity and simulation performance.
• Define and implement custom circuit verification checks and model QA flows.
• Develop automation and productivity tools using scripting languages to streamline simulation, verification, and data analysis.
• Help shape company-wide CAD infrastructure and best practices for analog, mixed-signal, and silicon photonics development.

What You Can Expect

Joining Marvell means working on technology that defines the future of computing and connectivity.

In this role, you can expect:

• Cutting-edge semiconductor technology — Work on advanced FinFET nodes and next-generation mixed-signal architectures.
• High technical impact — Your methodologies will be used across multiple product lines and engineering teams worldwide.
• Deep collaboration — Partner with world-class designers, modeling experts, and EDA innovators.
• Leadership without limits — Influence CAD strategy and engineering infrastructure across a global semiconductor organization.
• A culture of innovation — Marvell engineers push the boundaries of performance, efficiency, and integration.

You’ll also enjoy the energy of working in Silicon Valley’s semiconductor innovation hub in Santa Clara alongside engineers building the next generation of AI, networking, and cloud infrastructure silicon.

What We're Looking For

• BSEE with 10–15 years of professional experience, or MS/PhD in Electrical Engineering with 5–10 years of industry experience.
• Proven experience building and maintaining analog/mixed-signal design flows for advanced FinFET process technologies.
• Strong hands-on experience with industry-standard AMS simulation tools, such as:
  • Cadence ADE
  • AMS Designer
  • Spectre
  • Synopsys PrimeSim
  • AFS or equivalent
• Solid understanding of analog/mixed-signal design flows, including:
  • schematic capture
  • simulation
  • parasitic extraction
  • post-layout verification
• Strong understanding of device modeling and high-speed analog/RF simulation behavior.
• Experience debugging complex AMS simulation and modeling issues.
• Excellent communication skills and the ability to collaborate effectively with cross-functional teams.

Preferred Qualifications

• Experience with Cadence Virtuoso Schematic Editor, including:
  • PDK integration
  • CDF customization
  • netlisting infrastructure
• Knowledge of advanced circuit modeling techniques.
• Programming or scripting experience in:
  • Python
  • TCL
  • Perl
  • SKILL
• Experience developing custom CAD automation or verification frameworks.
• Familiarity with silicon photonics design flows.

Please note: This role is based in our Santa Clara office and requires onsite presence five days per week. Remote or hybrid work is not available for this position.

Expected Base Pay Range (USD)

150,680 - 225,700, $ per annum

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.


This role is eligible to participate in Marvell's bonus and equity plans, including a new hire equity grant and annual equity refreshers, ensuring you are rewarded for your contributions and remain invested in the company's long-term success.


Additional Compensation and Benefit Elements

Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life’s most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity 

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

#LI-AR3