MTS, Interface Pathfinding Hardware Development Engineer
Micron · Boise, United States · 4d ago
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
MTS, Interface Pathfinding Hardware Development Engineer
About the Role
At Micron, our vision is to transform how the world uses information to enrich life for all. As a global leader in memory and storage innovation, we develop technologies that accelerate intelligence and enable the next generation of high-speed interfaces.
Micron’s Interface Pathfinding team drives performance-scaling innovation across circuits, signaling, packaging, and interconnects with a 3–5 year technology horizon.
As the Interface Pathfinding Hardware Development Engineer, you will own characterization for a high-speed interface test-chip program: the characterization plan and its success criteria, development of the characterization bench hardware and its automation, the measurement-uncertainty budget, and the correlation report proving the silicon matches the models. You will join a small, senior team spanning analog design, layout, digital design, and verification, working closely with the Chip Lead and the Signal Integrity and Physical Design engineers — driving decisions independently while consulting heavily with other experts across Micron.
This is a foundational hire for a growing program. Strong execution early is expected to lead to follow-on projects of increasing scope, team size, and characterization complexity — including an expanding mandate for AI-enabled engineering leadership across the organization.
What You’ll Own
Characterization Planning
• Derive the electrical characterization plan from the architecture specification and SI link budget before RTL freeze, each test case traceable to a specification parameter and success criteria.
Design-for-Characterization
• Author observability and test-access requirements (debug registers, trim exposure, loopback and pattern modes, analog test-mux) into the register map before RTL freeze.
Measurement Infrastructure
• Develop and own the characterization architecture from hardware and test board specifications through to the automated data acquisition framework.
Measurement Uncertainty
• Measure, calibrate, and de-embed characterization hardware to isolate device performance from measurement noise.
Characterization
• Serve as the program’s expert across link and timing integrity, power delivery, I/O-ring robustness, environmental corners, and first-silicon bring-up.
Correlation and Debug
• Co-author the per-revision sim-to-silicon correlation report with the SI engineer and lead the debug tiger team when silicon deviates from simulation.
Tape-Out Readiness
• Sign the characterization-readiness items on the tape-out checklist, then author the post-silicon characterization report and the correlation-gap table for the next test chip.
Equipment Roadmap and Capability Building
• Define bench capability against target data rates, represent findings to vendors, standards forums, and management, mentor junior engineers, and contribute to the IP portfolio.
AI-Enabled Engineering Leadership
• Serve as the Interface Pathfinding organization’s primary resource for agentic-AI workflow design and deployment. Architect, implement, and document AI-assisted development and characterization pipelines — including characterization plan generation, data analytics, and predictive modeling via sim-to-silicon correlation acceleration. Represent Micron’s AI-enabled characterization methodology to external partners, standards bodies, and internal leadership.
What You Bring
Required
• MSEE with 10+ years (or BSEE with 12+ years) in semiconductor characterization or test engineering, including at least one program owned from plan through sign-off
• High-speed time-domain measurement including Rj/Dj separation and jitter transfer at multi-GT/s rates
• BERT and pattern generator/analyzer operation for link margining; switch-matrix automation with per-path de-skew
• Root Cause and Corrective Action through Principal Component Analysis and First-Principles Design of Experiments
• Instrument automation for characterization across corners and conditions
• PDN and load-transient measurement; judgment on bench reference-clock and supply-noise realism
• Development of simulation plans to pre-validate a test approach; design-of-experiments applied to characterization and root cause
• First silicon bring-up of an internally designed device
• Frequency-domain fixture de-embedding (VNA S-parameters, 2x-thru or TRL, TDR) correlated to field-solver models
• Technical representation of the engineering organization to customers or vendors
• Cross-organizational technical leadership: demonstrated track record of developing methodologies, tools, or frameworks adopted by engineering teams beyond the immediate program
• Agentic AI workflow construction and deployment including analysis, development, and automation
Preferred
• Pro-active, visionary, and collaborative, with clear written and verbal communication of complex technical issues
• Familiarity with silicon photonics and optical measurement techniques
• BER-bathtub extrapolation and eye-mask methodology; CTLE/DFE equalization effects on measured margin
• On-die calibration verification; on-die PDN impedance correlated to power-integrity simulation
• Split-lot process-corner characterization correlated to STA corners
• JEDEC or external-forum participation; technical presentation record
Why This Role
• End-to-end characterization ownership — from planning and bench development through silicon correlation and sign-off — on a program where your decisions are visible and your contributions immediately felt.
• You will work alongside world-class engineers — a small, senior team of genuine collaborators spanning analog, digital, layout, and signal integrity.
• The lean, senior team structure means your judgment is trusted; this is an individual contributor role with real impact, and a clear path to expanded scope and increasing technical ambition.
A Note to All Candidates
We are building a long-term, high-caliber team around a compelling PHY technology program — and looking for engineers who want to own something, build something, and grow with a program. If that description resonates, we’d like to hear from you.
As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
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