Senior/Staff Design Verification Engineer, HBM

The Heterogeneous Integration Group (HIG) sits within the Technology and Products Group (TPG). We are developing High Bandwidth Memory (HBM) solutions for AI and ML applications! We stack multiple DRAM chips on a high-speed memory controller using TSV (Through Silicon Via) technology, dramatically increasing memory density and bandwidth. Our designs span custom digital and RTL2GDS flows, and we are targeting the lowest power per bit in the industry.

Micron’s High Bandwidth Memory (HBM) Design Verification team is responsible for ensuring the functionality, performance, and quality of next‑generation memory products that enable advanced computing applications. As a Senior Design Verification Engineer, you will collaborate closely with design, architecture, and product engineering teams to verify complex, high‑density DRAM circuits and deliver robust, production‑ready designs. This role combines deep technical verification expertise with cross‑functional collaboration in a global environment.

You will be challenged by the complexity and difficulty of verifying high density memory chips (up to 32Gb) with huge scale of circuit capability (over 4M transistors), ultra-high speed designs, sophisticated functionality which includes next Generation DDR/LPDDR (ex: DDR5, LPDDR5) and advanced low power and power management technologies.

You will be responsible to evaluate the functionality and performance of the Full-chip and block-level circuit designs using different verification tools, techniques, and strategies. In addition, you will also need to provide solutions to help deliver a functionally accurate design.

Lastly, you will need to collaborate closely with Micron's various design, verification, and product engineering teams all over the world to ensure design project success.

Responsibilities

• Evaluate full‑chip and block‑level HBM and DRAM circuit designs to ensure functional correctness and performance.
• Develop verification plans from functional specifications in collaboration with architects and design teams.
• Create, enhance, and maintain verification environments, testbenches, test vectors, and regressions.
• Increase functional coverage across DRAM architectures and features using appropriate verification tools and methodologies.
• Debug design issues, support root‑cause analysis, track bugs, and drive coverage and closure.
• Apply mixed‑signal and digital verification techniques using industry‑standard simulation tools.
• Collaborate with global design, verification, and product engineering teams to ensure successful project execution.
• Lead verification efforts on assigned projects and mentor verification engineers who are developing their skills.

Minimum Qualifications

• Bachelor’s degree or equivalent experience in Electrical Engineering, Computer Engineering, or a related field.
• Solid understanding of CMOS circuit design fundamentals.
• 5 -7 plus years of experience with mixed‑signal and/or digital verification methodologies.
• Proficiency in SystemVerilog (or equivalent), including assertions (SVA), and verification methodologies
• Strong debugging, analytical, and problem‑solving skills with effective technical communication abilities.

Preferred Qualifications

• Experience with analog and digital simulation tools such as HSPICE, Verilog‑HDL, and FINESIM.
• Proficiency in scripting languages such as Python or Perl to support verification automation.
• Demonstrated technical leadership, including mentoring engineers and influencing verification strategies.
• Experience using AI-enabled or Generative AI solutions to accelerate verification planning, test development, coverage analysis, and root-cause debugging