Senior Principal Engineer, Physical Design Methodology & RTL-to-GDS Architecture

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.  

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions.  Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time. 

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Job Description:

Overview

As the Senior Principal Engineer of Physical Design Methodology, you will serve as the chief visionary and architect of the physical implementation backbone for our next-generation, high-frequency CPU cores. This is a highly strategic, cross-functional leadership role focused on pioneering AI-native, automated methodologies that push Power, Performance, and Area (PPA) beyond industry standard limits on sub-3nm (N3/N2) process nodes. You will act as the critical bridge between CPU micro-architecture and physical reality, driving early architectural trade-offs, shaping EDA tool roadmaps, and setting the technical standard for world-class, predictable execution across the organization.

Key Responsibilities

• Strategic Methodology Vision: Architect, validate, and mandate "Best-of-Class" RTL-to-GDS roadmaps tailored for ultra-high-frequency CPU implementation. Define the long-term methodology strategy for the entire physical design organization.

• Cross-Functional Architectural Influence: Partner directly with CPU Architects and RTL leads during the pathfinding phase. Drive early-stage PPA modeling and physical feasibility studies to influence micro-architectural decisions long before the RTL is frozen.

• AI-Native EDA Transformation: Spearhead the paradigm shift toward autonomous, ML-driven design optimization. Lead the strategic integration and global scaling of advanced AI/ML EDA platforms (e.g., Synopsys DSO.ai) to systematically navigate and solve the massive sub-3nm PPA design space.

• Industry-Level Partnerships: Serve as the foremost technical authority and executive interface with tier-one EDA partners (Synopsys) and IP/Foundry providers. Influence vendor product roadmaps, demand custom tool features, and co-optimize Standard Cell/SRAM library architectures for maximum PPA extraction.

• Advanced Hierarchical Architecture: Dictate the global floor planning, timing budgeting, and integration strategies for multi-million gate, highly complex hierarchical designs, ensuring systemic convergence across all blocks.

• Scalability & Engineering Excellence: Establish a culture of "Flows-as-Code." Design resilient build systems, automated telemetry dashboards, and rigorous execution protocols to achieve "push-button" predictability, effectively eliminating manual intervention at scale.

• Technical Mentorship: Serve as a mentor and technical guide to Principal and Senior engineers, elevating the overall technical competence and problem-solving capabilities of the engineering organization.

Requirements

• Industry Authority: 15+ years of extensive experience in Physical Design and Methodology, with a distinguished track record of driving the physical architecture and successful tape-outs of elite, high-speed CPUs (3GHz - 4GHz+).

• Education: Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science, VLSI, or a related highly technical field.

• Bleeding-Edge Node Expertise: Deep, authoritative understanding of sub-3nm device physics, parasitic effects, and design rules. Hands-on tape-out experience with TSMC N3 is strictly required; active pathfinding or exposure to N2/A14 generation nodes is highly preferred.

• Tool Ecosystem Mastery: Elite, power-user expertise across the Synopsys Fusion Design Platform (Fusion Compiler, IC Compiler II, PrimeTime), with the ability to look under the hood and debug core algorithmic tool behaviors.

• AI/ML Integration: Proven, demonstrable success in deploying ML-based design space optimization tools (DSO.ai, Cerebrus) in a high-stakes production environment to achieve measurable PPA gains.

• Systemic Automation: Expert-level software engineering mindset using Python, Tcl, or Perl. Proven ability to architect massive, scalable, and maintainable automation frameworks from the ground up.

• Deep Analytical Acumen: Unmatched expertise in solving extreme physical phenomena, including timing closure at ultra-low voltages, dynamic IR drop, complex electromigration (EM), and crosstalk challenges inherent to high-performance compute silicon.

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.