Server CPU Physical Design Integration Engineer, Staff level - Cambridge, UK

Company:

Qualcomm Technologies International Ltd

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Job Overview

Qualcomm is looking for an experienced CPU Physical Design Integration Engineer to join the Nuvia Data Center CPU team in Cambridge, UK. This team is focused on developing next-generation, high-performance, and power-efficient custom CPU technologies for advanced compute and server platforms, driving innovation across the industry.

In this position, you will play a key role in the physical design, integration, and verification of high-frequency CPU designs. You will collaborate closely with cross-functional teams, including microarchitecture, RTL design, CAD, circuit design, block-level physical design, and SoC-level physical design, to deliver production-ready designs.

Your responsibilities will span the full CPU physical design flow, including synthesis, floorplanning, partitioning, power planning, IP integration, clock and power distribution, reliability analysis, power and noise analysis, static and dynamic power integrity, layout verification, and electrical rule checking.

This role offers the opportunity to impact CPU architecture and design methodologies from early planning stages through implementation, signoff, and silicon validation.

The position is offered at the Staff Engineer level, with responsibilities, ownership, and technical leadership commensurate with your experience.

Key Responsibilities will include

As a Server CPU Physical Design Integration Engineer, you will:

• Own Final CPU Layout database Implementation, Integration and Verification of high frequency next-generation data center CPU designs.
• Driving block partitioning, floorplan implementation and pin placement strategies.
• Work with SOC team and other IP teams to ensure all technical, interface and integration requirements are met.
• Partner with CAD and physical design teams to develop and improve flows for chip-level integration, validation and analysis.
• Working collaboratively with project team members to identify and resolve issues which arise during the design cycle and take the key learnings into the next product cycle.
• For Staff-level candidates, provide technical leadership, mentor engineers, influence cross-functional methodology, and drive resolution of complex and critical Integration challenges.

Required Skills and Experience

We are seeking candidates with strong experience in CPU physical design implementation Domain, preferably with experience delivering complex, high-performance CPU designs.

The ideal candidate will have:

• Deep CPU-specific expertise across multiple areas of structural and physical design, including synthesis, timing closure, multi-power-domain analysis, structured placement and routing.
•  Experience collaborating closely with leading EDA vendors to develop, enhance, and optimize tool capabilities for designing high-speed, low-power, synthesizable CPU cores.
• Optimizes CPU design to improve product level parameters such as power, frequency, and area.
• Hands-on involvement in developing, refining, and automating physical design methodologies and implementation flows.
• Strong leadership and communication skills with the ability to work effectively with global, cross-functional distributed teams across architecture, RTL, CAD, circuit design, physical design, SoC, and verification disciplines.
• Proficiency in scripting and automation to improve productivity, debug efficiency, and design-flow scalability, including the adoption of GenAI-driven initiatives where applicable.
• Scripting to automate tasks and improve debug efficiency including genAI initiatives.
• Experience working with industry-standard EDA implementation and signoff flows for physical design, timing analysis, power analysis, and physical verification.

Minimum Qualifications

Candidates should typically have one of the following:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.

OR

• Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in hardware engineering, CPU design, physical design, clock design, or implementation.

OR

• PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field with relevant experience in CPU design, physical implementation, clock design, or circuit-aware methodology.

The role is intended for experienced candidates and is open for Staff Engineer level.

Preferred Qualifications

Experience in any of the following areas would be highly valuable:

• Experience leading or contributing to CPU, GPU, or large SoC physical design integration from early floorplanning through final GDS tapeout.
• Strong background in top-level or chip-level physical design, including floorplanning, partitioning, pin placement, power planning, clock distribution, IP integration, and final layout database assembly.
• Hands-on experience with hierarchical physical design methodologies, including top-down planning, budgeting, block integration, timing convergence, and physical convergence.
• Experience working with advanced semiconductor process nodes, especially 7nm and below.
• Strong understanding of place and route, clock tree synthesis, structured placement, routing optimization, congestion analysis, and design closure methodologies.
• Familiarity with power-aware implementation techniques, including multi-voltage domains, power gating, clock gating, IR drop mitigation, EM analysis, and power integrity closure.
• Experience integrating hard IP, memory macros, mixed-signal blocks, PLLs, clocking structures, and third-party IP into large-scale CPU or SoC designs.
• Ability to analyse implementation and signoff results, identify design bottlenecks, and drive improvements in power, performance, area, reliability, and manufacturability.
• Experience developing automation or analysis flows using TCL, Python, Perl, or similar scripting languages.
• For Staff-level candidates, demonstrated ability to lead technical initiatives, influence cross-functional teams, define methodology, and mentor other engineers.

What We Value

We are especially interested in engineers who:

• Have strong fundamentals in physical design, timing, power, routing, clocking, and layout verification.
• Enjoy solving complex integration challenges across floorplanning, partitioning, power planning, clock distribution, timing closure, physical verification, and tapeout readiness.
• Bring a structured, analytical, and data-driven approach to debug, convergence, signoff closure, and methodology improvement.
• Communicate clearly and effectively across microarchitecture, RTL, circuit design, CAD, timing, SoC integration, IP, and physical design teams.
• Are proactive in identifying risks, driving cross-functional issue resolution, and capturing learnings to improve future product cycles.
• Show technical curiosity and a continuous-improvement mindset, including the ability to automate repetitive tasks and improve debug efficiency.
• Can provide technical leadership while remaining hands-on in complex design closure and integration challenges.
• Thrive in a collaborative, fast-paced engineering environment where technical depth, execution quality, and cross-team partnership are essential.

Benefits and Perks

At Qualcomm, you will be part of a collaborative engineering culture focused on innovation, technical excellence, and meaningful product impact.

We offer:

• Competitive compensation package, including base salary, performance-related bonus, and equity opportunities.
• Employee Stock Purchase Plan and equity programs supporting employee share ownership and long-term participation in Qualcomm’s success.
• Pension and retirement support, including a matching pension scheme.
• Health and wellbeing benefits, including medical, life, income protection, and wellbeing resources.
• Maternity, paternity, family, and extended leave support to help employees balance professional and personal commitments.
• Education assistance and tuition support to enable continued learning and professional development.
• Relocation and immigration support where applicable, particularly for strong candidates moving to join the Cambridge team.
• Employee assistance and resilience programs supporting mental wellbeing, balance, and personal resilience.
• Opportunities to connect through employee networks, community programs, volunteering, and social groups that support inclusion, collaboration, and community engagement.
• Subsidised wellbeing and lifestyle benefits, which may include gym or fitness support, bicycle purchase schemes, and employee clubs.
• A flexible, collaborative, and technically challenging work environment, with the opportunity to work alongside highly skilled engineers on advanced CPU technology.

Why Join the Nuvia Data Center CPU Team in Cambridge?

 Cambridge is Qualcomm’s largest office in the UK, with approximately 400 team members across engineering, business strategy, and support functions. From an engineering perspective, the Cambridge site includes teams focused on RF and PMU analog design, digital design and verification, digital physical design, embedded software, packaging, and post-silicon validation. Target products include high-performance CPUs and GPUs, ultra-low-power IoT devices, and wearables such as smart glasses, smart watches, and earbuds.

The Nuvia Data Center CPU team is building advanced custom CPU technology for next-generation compute platforms. As a CPU Physical Design Integration Engineer, you will play a key role in taking complex CPU designs from Implementation through integration, verification and final tapeout readiness.

This role offers the opportunity to work on challenging aspects of CPU physical design integration, including floorplanning, partitioning, IP integration, power and clock distribution, timing convergence, physical verification, power integrity, and final layout database assembly. You will collaborate closely with architecture, RTL, CAD, circuit design, block-level physical design, SoC, and signoff teams to deliver high-frequency, power-efficient, manufacturable CPU products.

This is an opportunity to contribute to technically demanding data center CPU designs, influence physical design methodology across future product generations, and make a direct impact on world-class silicon products developed by a highly experienced engineering team in Cambridge.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

*References to a particular number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfill the principal duties of the role and possesses the required competencies.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

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