Data Center SoC Power & Limits Architect

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

• Define holisticpower, thermal, and electrical limits architecture across silicon, board, system, rack, and cluster levels
• Architectpower budgeting, allocation, and enforcement mechanisms across CPU, GPU, memory, accelerators, and I/O
• Develop strategies to maximize performance underdatacenter-level constraints (rack power caps, cooling limits, PUE targets)

• Architect advanceddynamic power control systems (e.g., DVFS/DCVS, AVS-like systems) for fast transient response
• Designclosed-loop control systems using telemetry and feedback to optimize performance vs. constraints
• Developproactive and reactive limit management (thermal throttling, power capping, workload shaping)

• Define requirements and interfaces fortelemetry infrastructure (sensors, BMC, firmware, system SW)
• Enablereal-time monitoring and decision making across system layers
• Ensure integration with platform controllers (e.g.,BMC/EC, rack management, orchestration layers)

• Collaborate with:
  • Silicon/SoC architects (power islands, regulators, sensors)
  • Platform teams (VRs, PDN, cooling)
  • Software/firmware teams (power management algorithms)
  • Data center infrastructure teams (rack-level optimization)
• Definehardware/software partitioning for limits enforcement with minimal overhead

• Develop system-level models (MATLAB/Simulink, architectural simulators) to:
  • Predict performance vs. power/thermal constraints
  • Evaluate algorithms and architecture trade-offs
• Performworkload-driven analysis to validate architecture decisions

• Drive innovations in:
  • Power delivery efficiency
  • Thermal-aware scheduling
  • AI workload-aware limits
  • Rack/cluster-level power orchestration
• Define next-generation architectures to supportscaling AI/HPC performance under constrained infrastructure

• 10+ years of experience in power architecture, system architecture, or related domains
• Deep expertise in:
  • Power management systems and limits control
  • Thermal and electrical constraints in high-performance systems
  • DVFS/DCVS, power capping, and control systems
• Strong understanding of:
  • Data center/server architecture (CPU/GPU/accelerators, memory systems)
  • Power delivery networks (VRs, PDN, rack power distribution)
  • Telemetry, sensors, and system monitoring
• Experience with modeling and analysis tools (e.g., MATLAB, Python)

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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Pay range and Other Compensation & Benefits:

$174,400.00 - $261,600.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.