GPU PD Engineer (Austin/San Diego)

This role involves the physical implementation of industry-leading integrated graphics core designs, from RTL to GDS, focusing on highly complex and high-frequency blocks or top-level designs. As a senior individual contributor, the candidate will utilize his/her proficiency in industry-standard tools and advanced technology nodes to enhance the Power, Performance, and Area (PPA) metrics of our continuously evolving GPUs. The objective is to optimize designs to meet stringent PPA targets. The candidate will work closely with RTL design and architecture teams to drive and devise innovative solutions for design optimization. The candidate will also work closely with multidisciplinary teams and tool vendors to develop and improve automation in design flows and methodologies, enhancing efficiency. This position demands a comprehensive understanding of the trade-offs in Power, Performance, and Area (PPA) to make informed decisions that achieve optimal design solutions.

The ideal candidate will have/demonstrate the following:

• Experience in Physical design implementation which includes floor-planning, placement, clock implementation, routing for complex, high frequency designs
• Experience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus
• Must have good working knowledge of static timing analysis, reliability and power analysis and PDN network
• Strong understanding of CMOS stdcell and memory circuits and design techniques to push Power, Performance and Area of complex designs
• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks
• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance
• Proven track record of innovation, with the ability to independently tackle and resolve complex technical challenges
• Solid working knowledge of scripting skills including tcl, perl or python
• Excellent communication skills and collaborating in a team environment is a must
• Proven track record of collaborating with diverse teams to drive and resolve complex technical challenges.
• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure leading to successful tape-outs
• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff
• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area
• Hands on experience working with sub-micron technology process nodes eg. 4nm and below is highly advantageous
• Prior experience in flow and methodology development is an advantage
• Demonstrated history of successful innovation with notable accomplishments
• Proficiency in reading and understanding RTL (Verilog/System Verilog)
• Possess excellent debugging and analytical skills, coupled with strong leadership abilities to drive solutions among various teams
• Self-motivated, excellent time management, and strong organizational skills
• Ability to work well in a collaborative environment with multi-disciplined teams 

Minimum Skills:

• Bachelor’s degree in Electrical/Computer Engineering
• 17+ years of direct synthesis and physical design work experience

Preferred Skills:

• Master’s degree in Electrical/Computer Engineering
• 15+ years of direct synthesis and physical design implementation work experience
• In depth end to end experience from RTL2GDS, taping out at multiple complex designs in deep sub-micron technology nodes

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