Signal Integrity Architect, PCB Modeling & Automation

The Qualcomm Data Center team is developing high-performance, energy-efficient server solutions for data center applications. We are looking for highly talented, innovative, and collaborative individuals to join our advanced platform engineering work.

Our Mission

We are dedicated to transforming the industry by reimagining silicon and developing next-generation computing platforms. You will collaborate with world-class engineers to create solutions that advance performance, energy efficiency, and scalability. Our focus is on Qualcomm data center reference platforms that bring together hardware, software, reference designs, user guides, SDKs, and related enablement collateral.

Position Summary

We are seeking a Signal Integrity Architect to own PCB modeling methodology, channel-modeling capabilities, model requirements, automation strategy, and model-quality standards across Qualcomm data center server platforms. This role directly develops critical models and automation flows and technically leads or reviews modeling work performed by matrixed engineering teams, partners, and EDA vendors. The architect also provides direct SI ownership for LSIO/GPIO interfaces and modeling support for TPPHY, working with interface architects, board and layout teams, package and silicon organizations, and validation engineers to deliver accurate, reusable models and decision-grade analysis across the platform.

Key Responsibilities

• Own and directly develop scalable 3D full-wave and 2.5D modeling flows for PCB structures, including scripted geometry setup, parameter sweeps, batch simulation, model extraction, and results processing.

• Create and qualify reusable S-parameter and other applicable models for PCB traces, vias, breakouts, connectors, and related channel structures across assigned platform interfaces.

• Define modeling work packages, required inputs, model-quality checks, convergence criteria, correlation methods, acceptance criteria, documentation requirements, and release practices for work performed within SPE or by supporting engineering teams.

• Partner with PCIe/CXL, LPDDR, validation, package, board, and layout teams to translate interface requirements into accurate PCB and full-channel modeling plans.

• Provide stackup, material, routing, via-transition, return-path, termination, and component-placement guidance based on simulation results.

• Translate modeling results into platform-level design constraints, trade-off recommendations, and model-acceptance decisions for interface architects, board teams, and layout teams.

• Own SI analysis and design guidance for LSIO/GPIO interfaces, including SPI, I3C, and proprietary parallel interfaces, and provide SI analysis and modeling support for TPPHY.

• Coordinate with CHS on package-model inputs and model interfaces; integrate qualified package inputs into platform-level channel analysis without assuming ownership of package architecture or extraction methodology.

• Partner with the validation engineer to correlate models with VNA, TDR, oscilloscope, and other applicable measurements and resolve model-to-hardware discrepancies.

• Develop automation, data-reduction, visualization, regression, and reporting tools that improve analysis productivity, repeatability, traceability, and scalability.

• Technically lead and review modeling work performed by matrixed engineering teams, partners, and EDA vendors; improve solver workflows, compute utilization, model interoperability, and tool deployment.

• Prepare technical documentation, modeling guidelines, review material, and recommendations for engineering teams, leadership, customers, suppliers, and ODM partners as appropriate.

• Mentor validation and SI engineers in PCB and channel-modeling methods, automation practices, and model-quality evaluation to build broader team capability.

Qualifications

• Master's degree in Electrical Engineering, Computer Engineering, Applied Physics, or a related field.

• 8+ years of experience in signal integrity analysis, electromagnetic simulation, PCB/package modeling, or high-speed digital system development.

• Strong knowledge of computational electromagnetics, transmission-line theory, S-parameters, impedance, loss, crosstalk, return paths, and frequency-domain and time-domain channel analysis.

• Hands-on experience with 3D full-wave and 2.5D EM simulation, including ports and boundaries, meshing, convergence, parameter sweeps, and model extraction.

• Proficiency with one or more relevant simulation environments, such as ANSYS HFSS/HFSS 3D Layout/SIwave, Cadence Clarity/Sigrity, Dassault Systemes CST, or Keysight ADS.

• Experience modeling PCB traces, via structures, breakouts, connectors, and other package-to-board or board-level channel elements.

• Experience automating EDA and data-analysis workflows using Python or a comparable scripting language in Unix/Linux environments.

• Experience validating model accuracy through solver cross-checks, design experiments, or correlation with laboratory measurements.

• Working knowledge of PCB stackups, materials, fabrication processes, layout constraints, and manufacturing tolerances.

• Experience with LSIO/GPIO interfaces or demonstrated ability to apply SI principles across both high-speed and lower-speed digital interfaces.

• Ability to work independently and collaboratively across interface, package, board, layout, and validation teams.

• Strong written, verbal, and presentation skills.

Preferred Qualifications

• Ph.D. in Electrical Engineering, Computer Engineering, Applied Physics, or a related field.

• 12+ years of experience in PCB and channel modeling, SI methodology development, simulation automation, and model validation.

• Demonstrated experience building production-quality modeling automation pipelines for parametric simulation, batch execution, extraction, regression, and reporting.

• Experience generating and qualifying broadband S-parameter models for PCB and package-to-board structures.

• Experience correlating models with VNA, TDR, and oscilloscope measurements and designing fixtures or coupons for correlation.

• Experience with channel simulation and model interfaces used for PCIe/CXL, DDR/LPDDR, or other high-speed interfaces, without requiring primary interface-architecture ownership.

• Experience with Cadence Allegro or comparable PCB design and layout tools.

• Experience with distributed compute environments, job schedulers, version-controlled modeling flows, or continuous regression systems.

• Experience developing server, AI, HPC, data center, or other high-performance computing platforms.