3D Memory Chip Architect and Design, Principal Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm is a company of inventors that unlocked edge AI and connected computing ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform edge AI and connected computing potential into world-changing technologies and products. This is the Invention Age - and this is where you come in.

The Qualcomm Custom Memory Team in Process & Package Solutions Group has an opening in the areas of 3D Memory Design and Architecture for memory-centric compute systems for data center, mobile, compute, and XR. The candidate will assess and optimize the 3D Memory architectures to improve system KPIs such as bandwidth, latency, power, thermal, and area efficiency. The candidate will explore the best organization of near-memory processing units along with the system and memory buses so that the extreme bandwidth of 3D Memory will be fully utilized across the compute fabric for cloud, compute, mobile and IoT as well as studying how to interconnect those memory cubes using scale-up and scale-out fabrics. The candidate will work on solutions on 3D integration of both memory and compute blocks in power, thermal, and 3D fabric restrictions. The candidate is expected to understand the concepts of memory bank organization and signaling, bus, IO, and compute fabrics as well as advanced packaging and 3D integration. This position offers the opportunity to work across multiple organizations such as process and packaging team, AI and compute architects, memory controller team, global SoC team, performance modeling teams, and emulation team. Providing timely feedback and updating architecture and design trade-offs to the team is essential.

Responsibilities:

• Develop and optimize 3D DRAM/FLASH organization and near-memory computing architectures to achieve high density, high TOPS/mm2, and high TOPS/W
• Develop and validate models for 3D Memory performance, power, and yield as function of bank, TSV, and power distribution choices
• Develop novel fabrics for best/robust distribution of high-bandwidth data from 3D DRAM memory arrays to the near-memory computing units across various workloads for mobile, compute, and XR applications
• Develop power distribution topology that enable robust memory operation in the 3D stack
• Simulate and emulate system performance of 3D memory architecture choices across AI, compute, and mobile workloads
• Floorplan 3D memory chips and design memory array control structures under 3D integration manufacturing constraints, testability, repairability, and high performance
• Knowledge about chip connection fabrics such UCIe, UAL, LPDDR, HBM3/4 and PCIe

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications: 

• Experience in RTL, circuit and system design to be able to model and optimize dataflow
• Experience in SoC architecture and power/clock/bus design
• Experience in DRAM/FLASH architecture performance assessment
• Experience in memory circuit design (SRAM/DRAM/FLASH/ROM/OPT, etc)
• Experience in programming language (C/C++/Phyton) or scripting language (Perl/Python)
• Ability to develop Verilog/Verilog-A/Verilog-AMS models of critical dataflow is strong plus
• Familiar with the DRAM/FLASH datasheets and IO interfaces
• Experience in ASIC design, mixed-signal design, and performance modeling
• Good knowledge of memory architecture, buses, and 2.5D/3D integration
• Proficiency in use of EDA tools, Matlab, and Phyton
• Master's or Ph.D. in Electrical Engineering, Computer Science, or a related field

Soft Skills:

• Self-Starter with good communication skills and team-working spirit
• Strong problem-solving and analytical skills
• Ability to work independently and as part of a team

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$200,000.00 - $300,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.