SoC Physical Design CAD Engineer (Staff/Sr Staff)
Qualcomm · Bangalore, India · 18d ago
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 6+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 5+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.
Job Overview
We are looking for a Staff Engineer – Physical Design CAD to drive the development, deployment, and support of Physical Design methodologies, flows, and automation for complex SoC programs. The role involves enabling scalable PD infrastructure, improving design productivity, and partnering with PD, STA, DFT, and EDA teams to deliver best-in-class implementation solutions.
Key Responsibilities
Develop and maintain Physical Design flows covering Floorplanning, PnR, CTS, Routing, IR/EM, and Signoff.
Build automation and infrastructure using Tcl, Python, Perl, and Shell scripting to improve design efficiency and turnaround time.
Drive methodology improvements for timing, power, area, and design convergence across multiple SoC projects.
Collaborate with PD, STA, CAD, and EDA vendors to evaluate and deploy new tools and technologies.
Debug flow, tool, and methodology issues and provide scalable solutions across projects.
Drive flow validation, regression automation, and deployment across advanced technology nodes.
Provide technical leadership and mentor junior engineers.
Minimum Qualifications
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
7+ years of experience in Physical Design CAD, Methodology, or Design Automation.
Strong understanding of Physical Design implementation and signoff flows.
Expertise in Tcl, Python, Perl, and Linux environments.
Experience with industry-standard EDA tools from Cadence and/or Synopsys.
Preferred Qualifications
Experience with advanced technology nodes (7nm and below).
Knowledge of STA, IR/EM, Power Integrity, and Physical Verification flows.
Exposure to AI/ML-driven design automation and flow optimization.
Strong problem-solving, collaboration, and technical leadership skills.
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