CPU Verification Engineer (Staff/Senior Staff) - SV, UVM experts

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > Hardware Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.

Minimum Qualifications:

• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.

Role Overview

We are seeking a highly motivated and technically strongStaff Engineerto drive end-to-end verification of next-generationCPU Co-Processor (CPUCP/PDP) Power Management firmware and hardware features. This role requires deep expertise in SystemVerilog-based verification, power management validation, and cross-functional leadership across Firmware, RTL Design and Post-Silicon teams.

The ideal candidate will own verification strategy from architecture definition through signoff, driving quality, scalability, automation, and execution excellence across CPU programs.

Key Responsibilities

• Lead theend-to-end verificationof CPUCP/PDP firmware-driven hardware features, with a focus on Power Management, Reliability, and System Readiness.

• Architect and developrobust SystemVerilog/UVM testbenches, transactors, checkers, and verification infrastructurefor complex SoC subsystems.

• Drive verification of AMBA-based system IPs includingtimers, mailbox, interrupts, and interconnect fabrics (NoC).

• Own verification planning, test strategy, coverage modeling, coverage closure, and functional signoff.

• Define and implement comprehensive validation for power-management features such asDVFS, Low Power Modes (LPM), clock/power transitions, and firmware-controlled sequences.

• Lead complex debug and root-cause analysis acrossFirmware, RTL, Design, Emulation, and Post-Silicon teams.

• Develop reusable stimulus frameworks, automation solutions, debug utilities, dashboards, and productivity tools to improve execution efficiency and scalability.

• Support platform bring-up, SoD readiness, feature qualification, HW/FW release validation, and silicon readiness activities.

• Influence architecture reviews and verification methodologies, ensuring best practices are consistently applied across programs.

• Mentor junior engineers and foster a culture of technical excellence, ownership, and innovation.

• Drive cross-functional initiatives spanning Firmware, Hardware Design, Emulation, and Post-Silicon Verification teams.

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field .

• Extensive experience inSoC, CPU or Power-Management verificationenvironments.

• Strong expertise inSystemVerilog/UVM, verification methodologies,and testbench architecture.

• Proven experience developingNoC transactors, protocol checkers, and verification infrastructure.

• Deep understanding ofAMBA protocolsand system-level IPs such as timers, mailboxes, interrupts, and memory-mapped peripherals.

• Strong background inRTL simulation, emulation, waveform analysis, debug methodologies, and coverage closure.

• Experience validating power-management technologies includingDVFS, LPM, idle states, power sequencing, and reset flows.

• Proficiency inC/C++, SystemVerilog, Python, scripting, automation, and data-driven verification workflows.

• Strong analytical and debugging skills with the ability to diagnose issues across HW, FW, and system domains.

• Demonstrated ability to lead technical discussions, influence verification strategy, and drive execution across geographically distributed teams.

• Added Advantage: Power Aware verification and Gate level simulation Hands – On experience

Preferred Qualifications

• 8–12+ years of industry experiencein CPU, GPU, SoC, or complex subsystem verification.

• Proven expertise inpre-silicon verification methodologies, testbench architecture, and verification infrastructure development.

• Strong track record of delivering verification signoff for complex SoC features from architecture definition through silicon bring-up.

• Hands-on experience with automation frameworks,, regression infrastructure, and CI/CD verification workflows.

• Knowledge of system level Power management scenarios.

• Previous experience mentoring engineers and leading cross team technical initiatives across organizations.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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