CPU Physical Design Engineer, Staff

Job Overview

We are looking for bright and highly motivated ASIC Physical Design Engineers with strong analytical and technical skills to join our Snapdragon CPU team. This is an exciting opportunity to work on high-performance CPU designs for advanced SoCs in sub-10nm technologies targeting Mobile, Compute, and IoT products. Similar responsibilities are reflected in internal CPU Physical Design roles focused on RTL-to-GDSII implementation, PPA optimization, timing closure, and advanced-node design.

Key Responsibilities

• Own and drive block-level physical design implementation from RTL/netlist to GDSII.

• Perform Place & Route (PnR), timing closure, power optimization, physical verification, and signoff activities.

• Develop and optimize implementation methodologies, flows, and recipes to achieve best-in-class Performance, Power, and Area (PPA).

• Create and execute design experiments to evaluate implementation strategies and drive QoR improvements.

• Analyze, compare, and track implementation metrics to guide project decisions.

• Collaborate closely with RTL Design, Synthesis, STA, Power, Thermal, and Verification teams to achieve aggressive PPA goals.

• Debug and resolve implementation challenges related to timing, power, congestion, and physical verification.

• Contribute to methodology improvements, automation, and flow enhancement using scripting.

Minimum Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field.

• 7+ years of experience in ASIC Physical Design and high-performance CPU implementation.

• Strong experience in RTL-to-GDSII implementation flow.

Preferred Qualifications

• Extensive hands-on experience with Place & Route using Cadence Innovus and/or Synopsys Fusion Compiler. Relevant skills commonly include floorplanning, placement, CTS, routing, timing closure, and PPA optimization.

• Strong understanding of complete ASIC implementation flow, including:

  • Floorplanning

  • Power Planning

  • Placement

  • Clock Tree Synthesis (CTS)

  • Routing

  • Timing Closure

  • Physical Verification and Signoff

• Experience with STA and timing signoff using PrimeTime and/or Tempus.

• Expertise in SDC constraint generation, validation, and debugging.

• Experience with multi-power domain designs and UPF/CPF implementation.

• Good understanding of low-power design and implementation techniques.

• Knowledge of formal verification tools such as Formality and/or Conformal.

• Familiarity with IR/EM analysis, signal integrity, and power analysis.

• Strong scripting skills in Tcl, Perl, and/or Python.

• Experience working on advanced technology nodes (7nm and below preferred).

• Understanding of CPU microarchitecture and critical timing paths.

• Experience implementing high-frequency, high-performance CPU designs.

• Strong knowledge of clock architecture and CTS methodologies for high-speed designs.

• Exposure to constraint management tools and Verilog coding.

• Excellent debugging, problem-solving, and communication skills.