Heterogeneous Integration Physical Design Engineer, Staff
Qualcomm · Hsinchu City, Taiwan · 1mo ago
Company:
Qualcomm Semiconductor LimitedJob Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.
Key responsibilities:
- Design and mask layout of test chips for heterogeneous integration, custom DRAM, silicon components, and passive device development.
- Technology benchmarking, design flow, and PDK development for heterogeneous integration.
- Foundry interface and design support for System-Technology Co-Optimization (STCO).
- Layout and design analysis for advanced technology benchmarks
- Custom layout analysis for product issue debugging.
Desired Skillset/Experience:
Mask layout, OPC experience
Physical design and layout experience in sub-10nm silicon technology; hybrid-bonding, u-bump, RDL, and advanced packaging-related work experience is a plus.
Test chip design and execution experience.
Physical verification and PDK development experience (PEX, DRC, LVS).
DFM development experience.
Custom layout experience (Calibre, Cadence), svrf, tcl scripting
Advanced node process integration and unit process development experience is a strong plus.
Keywords :
Heterogeneous integration, hybrid bonding, 3DIC, PDK, Physical verification, mask layout design, DRC, DFM, physical design, svrf
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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