CPU STA/Timing Engineer (Lead/Staff/Sr Staff)
Qualcomm · Bangalore, India · 1mo ago
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 1+ year of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field.
As a CPU Physical Design Timing (STA) Engineer, you will be a key contributor to high‑performance CPU core and uncore designs, working closely with CPU microarchitecture, RTL, CAD, and physical design teams.
You will drive timing analysis and closure for complex, multi‑GHz CPU designs across block, cluster, and full‑chip hierarchies, ensuring aggressive frequency and power targets are met.
Roles and Responsibilities
Work closely with CPU microarchitecture, RTL, and DFT teams to understand CPU pipelines, critical paths, and performance goals, and to define, implement, and validate timing constraints.
Perform STA for high‑performance CPU designs at block, cluster, and SoC/top‑level hierarchies across multiple modes, corners, and scenarios.
Analyze timing on frequency‑critical CPU paths (core, cache, interconnect, clocking) and collaborate with RTL and DFT teams to drive logic and micro‑architectural fixes.
Provide actionable timing feedback to block‑level and top‑level physical design engineers to enable CPU frequency and timing closure.
Partner with CAD and methodology teams to develop, deploy, and enhance CPU‑specific timing flows and infrastructure.
Generate and review timing ECOs (logic and physical) to close setup, hold, noise, and cross‑talk violations in CPU designs.
Contribute to CPU timing methodology definition, best practices, and documentation for consistent signoff quality.
Preferred Qualifications
MS degree in Electrical Engineering with 3+ years of hands‑on experience in STA and timing closure.
Strong experience with STA and timing closure for high‑performance CPU or processor‑class SoCs.
Expertise in multi‑clock, multi‑domain CPU designs with aggressive frequency targets.
Experience in deep sub‑micron technology nodes and advanced process technologies.
Proven experience performing STA on large CPU/SoC designs with multi‑scenario and signoff‑quality closure.
Hands‑on knowledge of timing ECO techniques and their implementation for CPU frequency closure.
Solid understanding of standard cell libraries, CPU‑critical path optimization, and timing trade‑offs.
Familiarity with circuit modeling, transistor fundamentals, and worst‑case corner selection for CPU timing signoff.
Strong understanding of industry‑standard synthesis, place & route, and tape‑out flows.
Excellent communication skills to work effectively with CPU architects, RTL designers, PD, and CAD teams.
In‑depth knowledge of timing effects such as noise, cross‑talk, OCV/variation, and their impact on CPU designs.
Working knowledge of CPU/SoC architecture and HDL languages such as Verilog.
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