Manager, SoC Systems Validation Engineering (SVE)

Company:

QUALCOMM SEMICONDUCTORES Y SISTEMAS AVANZADOS DE BAJA CALIFORNIA

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

About Qualcomm

Qualcomm is a global technology leader driving innovation in wireless communications, AI, computing and connected systems. Our engineering teams develop industry-leading silicon, software, FPGA prototyping platforms, emulation systems and validation solutions that enable the next generation of mobile, automotive, AI and edge computing products. The Tijuana design center is a growing part of that engineering footprint, working shoulder to shoulder with teams in San Diego and across our global sites on the same leading-edge SoC programs.

Role Summary

We are looking for a senior technical leader to establish and grow SoC Systems Validation Engineering at our Tijuana site. This is a hands-on leadership role at the Senior Staff or Principal level: you will set the technical direction for system validation content, own delivery commitments for the silicon programs the site supports, and build a local team of validation and debug engineers from an initial core group into a self-sufficient organization.

The scope spans the full silicon lifecycle.

On the pre-silicon side, you will drive validation readiness on simulation, emulation and FPGA prototyping platforms. On the post-silicon side, you will lead bring-up, system-level validation, failure analysis and silicon debug in the lab, along with power, performance and concurrency characterization across CPU, DDR, NoC and peripheral subsystems. You will also own the infrastructure behind that work: test content frameworks, automation, CI/CD pipelines, lab enablement and the analysis tooling that turns raw failures into root cause. 

Because the team is being built, the role carries an unusual mix of technical depth and organizational work. You will interview and hire, mentor engineers at every level, define the local skills ramp, partner with university and industry recruiting channels in the region, and represent the Tijuana team in program reviews with architecture, design, firmware and software counterparts in other sites. Success is measured as much by the capability the site holds a year from now as by the silicon shipped this quarter.

Key Responsibilities

Technical leadership

· Own the system validation strategy for the SoC programs supported from Tijuana, from validation planning and coverage definition through sign-off criteria and exit reviews.

· Set the technical bar for test content, debug methodology and automation, and personally lead the hardest debug efforts rather than delegating them.

· Drive hardware and software co-debug across SoC architecture, firmware, drivers, kernel and hardware interfaces, taking issues to root cause and to a verified fix.

· Review and approve architecture and design decisions from a validation standpoint, including debug hooks, observability, trace infrastructure and bring-up sequencing.

· Apply AI-assisted workflows and automation to triage, failure clustering and regression analysis so that engineering effort concentrates on genuinely new failures.

Program execution and delivery

· Commit to and deliver the site's validation milestones: pre-silicon readiness, tape-out support, first-silicon bring-up, characterization windows and production release gates.

· Plan capacity and staffing against the program roadmap and negotiate scope with partner sites when demand exceeds the team's bandwidth.

· Establish and run the site's lab operations for validation: equipment planning, board and platform inventory, remote lab access, and safe, efficient shift coverage during bring-up.

· Report status, risks and quality metrics to program and engineering leadership with enough specificity that decisions can be made from them.

Team building and people leadership

· Recruit, interview and hire validation, debug and infrastructure engineers for the Tijuana team, from new graduates through senior staff.

· Define and run the onboarding and technical ramp for new engineers so that a new hire reaches independent debug capability on a defined timeline rather than by osmosis.

· Mentor engineers on silicon debug, low-level software and system architecture, and grow the next layer of technical leads within the site.

· Set clear goals and expectations, give direct and regular feedback, and support career growth and retention in a competitive regional talent market.

· Build the site's engineering culture: documentation, design and code review discipline, post-mortems on escapes, and knowledge sharing across shifts and sites.

Cross-site and cross-functional collaboration

· Act as the single technical point of contact for the Tijuana SVE team with architecture, design, verification, firmware, software, emulation and product engineering teams in other sites.

· Work across time zones with distributed counterparts, including hand-off practices that keep bring-up moving around the clock.

· Partner with EDA, emulation and instrumentation vendors on tooling, methodology and escalations.

· Represent the site in methodology forums, drive reusable content and flows back into the wider organization, and adopt what other sites have already proven rather than rebuilding it locally.

Minimum Qualifications

· Bachelor's degree in Computer Engineering, Electrical Engineering, Computer Science or a related technical field, with 10 or more years of relevant industry experience; or a Master's degree with 8 or more years.

· Deep experience in SoC or system validation, silicon bring-up and system debug, with direct ownership of at least one silicon program from pre-silicon readiness through production release.

· Demonstrated technical leadership of a validation or debug team, including mentoring, work assignment and delivery accountability. Formal people-management experience is valued but a strong technical lead ready to step into hiring and team building will be considered.

· Strong low-level programming skill in C/C++ and Python on Linux, including bare-metal or driver-level work.

· Working knowledge of SoC architecture: CPU subsystems, DDR and memory hierarchy, NoC and interconnect, clock and power management, low-power modes, and peripheral interfaces.

· Hands-on lab and debug experience with JTAG, trace, logic analyzers, oscilloscopes and kernel debuggers.

· Professional working proficiency in English and in Spanish, sufficient to lead a local team and to work daily with counterparts in the United States and other global sites.

· Legal authorization to work in Mexico and the ability to work on site in Tijuana with lab access.

Preferred Qualifications

· Master's or PhD in Computer Engineering, Electrical Engineering, Computer Science or a related field.

· Experience standing up a new engineering team or site function, including hiring plans, ramp plans and cross-site work-split negotiation.

· Experience with pre-silicon platforms: RTL simulation, emulation on Palladium or Veloce, and FPGA prototyping platforms such as RUMI.

· Power and performance characterization experience: Vmin and Fmax, thermal behavior, bandwidth, latency, QoS and concurrency analysis at the system level.

· Familiarity with DFT and manufacturing validation concepts such as MBIST, ATPG, scan-based debug, yield analysis and silicon characterization.

· Experience building validation automation and CI/CD pipelines and applying AI or machine learning to triage and regression analysis.

· Prior experience working with or within a Mexico-based engineering site, and familiarity with the regional university and talent ecosystem.

Core Technical Skills

The role does not require equal depth in every area below, but the successful candidate will be strong in silicon validation and debug and conversant across the rest, since the Tijuana team is expected to cover this full span as it grows.

Area Skills and Tools 

Programming and software 

C/C++, Python, Tcl, Perl, shell scripting; embedded Linux, device drivers and bare-metal firmware; software design, code review and automation practice 

Hardware and SoC 

SoC architecture; RTL and Verilog / SystemVerilog literacy; hardware validation and debug; performance and power analysis; FPGA design 

Silicon validation and debug 

Pre-silicon and post-silicon bring-up; failure analysis and root-cause debug; platform-level debug; JTAG and trace-based debug; PVT and marginality analysis; AI-assisted debug automation 

Power and performance 

Power characterization; thermal analysis; Vmin and Fmax characterization; CPU, GPU, DDR and NoC analysis; low-power design methodology 

Pre-silicon platforms 

RTL simulation; emulation on Palladium and Veloce; FPGA prototyping and RUMI; emulation build generation; platform bring-up; timing closure and deployment flows 

Infrastructure and tooling 

Validation frameworks and scalable test content; CI/CD automation; Git; JIRA; lab equipment and remote lab access; data analysis and reporting 

What Success Looks Like / Horizon / Expected outcome 

First 90 days... 

Understand the supported programs and their validation plans, take ownership of a defined validation scope, establish the hiring plan and interview loop for the site, and set up the local lab and infrastructure needs. 

Six months...

A functioning core team is hired and onboarded, the site owns end-to-end validation for at least one defined subsystem or program area, and the team is closing its own debug findings without routine escalation. 

Twelve months...

Tijuana is a recognized delivery partner on program milestones: validation content is developed locally, automation and CI/CD are in place, and the site contributes methodology improvements back to the wider organization. 

Beyond...

The team scales to cover additional programs and domains, with local technical leads mentoring new engineers and a durable hiring pipeline in the region. 

Why Join Us

· Work on industry-leading mobile, AI, automotive and computing SoCs from the first RTL drop through production silicon.

· Take founding ownership of a validation team at a growing site, with the visibility and latitude that comes with building something rather than inheriting it.

· Collaborate with world-class engineers across hardware, software, FPGA, emulation, validation and debug domains in San Diego and around the world.

· Solve challenging technical problems that span the entire silicon development lifecycle, with access to advanced development platforms and large-scale engineering infrastructure.

Build the future of AI and mobile computing in Tijuana. From silicon bring-up and system validation to debug, emulation and validation infrastructure, this is the chance to shape a new engineering team at the center of Qualcomm's silicon development.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.

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