SoC Clock & Power Management Validation Lead, Staff (AI Accelerator Platform)

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Qualcomm’s System Validation & Emulation (SVE) team is part of the central SoC validation organization responsible for ensuring end-to-end silicon quality across pre- and post-silicon phases.

This role focuses on content quality and system-level validation enablement, offering deep exposure to Qualcomm SoCs through bare-metal validation content, scalable automation frameworks, and complex system debugs. Engineers in this role work across HW and SW boundaries to develop, validate, and scale system-level test content, ensuring high-quality silicon validation across a wide range of SoC domains.

Excellent Opportunity to work on cutting-edge SoCs across multiple product segments, including:

• Premium mobile and flagship platforms
• Data center
• AI Accelerator platform

Role Overview:

Lead end-to-end validation of clock, power, reset, and power-management architectures for next-generation AI accelerator platforms. Drive pre-silicon and post-silicon validation of Clocking infrastructure, PMIC integration, DVFS, and low-power features across complex multi-die AI systems. Partner closely with Architecture, Design, Verification & Firmware teams to debug and root-cause power, performance, stability, and scalability issues. Define validation methodologies, stress workloads, and automation frameworks to ensure robust operation under demanding AI training and inference scenarios. Own power subsystem bring-up readiness and delivery of production-quality silicon across all program milestones

An ideal candidate combines expertise in Clocking, DVFS, Power Management, PMIC, Firmware, Silicon Bring-up, and AI/HPC platform validation

Roles & Responsibilitie

• Own the E2E bare metal framework validation SoC clock and power architectures
• Validation planning – understand design changes, visualize standalone and system level test requirements and scenarios
• Test plan development – clearly document test strategy and dependencies
• Conduct validation strategy and test plan review with all stakeholders – architects, designers, verification engineers, software engineers
• Develop scalable device drivers, standalone and system tests using C
• Debug complex issues both on pre-Si and post-Si platforms, provide debug direction
• Review validation platform schematics to ensure post-Si debug support – might have to work with platform design team
• Automate validation process – development, execution, inference using python, perl, shell
• Use lab instruments – multimeter, oscilloscopes , logic analyzer
• Efficiently collaborate with teams in different time zones – both internal and external

Minimum Requirements:

• Bachelor’s degree in engineering (electronics, computer engineering etc.)
• 5+ years of relevant experience in SoC validation and / or associated areas (SW development, embedded systems etc.)
• Prior work experience in clock/ power validation
• Proficient in C, Python
• Experienced in using lab instruments – multimeter, oscilloscopes , logic analyzers
• Exposure to debug tools (JTAG etc.). Knowledge of debug methodology of ARM based SoCs
• Very good at problem solving - analytical and debugging skills

Preferred Qualifications:

• Prior exposure to below SW skills would add an edge above other applicants:
  • Experience with Cross-Compilers, Linkers and makefiles
  • Understanding of coherency and concurrency in modern SoC architecture
• Knowledge of PMIC/ prior experience in validating rail power (power measurement tools/ setups)
• Knowledge of pre-Silicon validation and debug on FPGA based emulation platforms is a plus
• Knowledge of RTL and HDLs (Verilog/ System Verilog) would be an additional advantage
• Should have prior work experience in a cross functional matrix work environment

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$145,600.00 - $218,400.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm.  We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus).  In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.

If you would like more information about this role, please contact Qualcomm Careers.