AI System Architect (NPU / GPU / Interconnect)
Qualcomm · Shanghai, China · 5h ago
Company:
Qualcomm China
Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
We are seeking experienced architects with deep expertise in AI accelerators (NPU), GPUs, and/or high-performance system interconnects to define next-generation AI and data center compute platforms.
Successful candidates will possess strong architectural knowledge in one or more of the following areas:
- AI accelerator and NPU architecture
- GPU architecture, graphics, and compute systems
- High-performance system interconnects and data center fabrics
Key Responsibilities
Customer & Platform Architecture
- Engage with customers, partners, and internal stakeholders to understand AI workload requirements, deployment scenarios, performance targets, and system constraints.
- Translate customer and market requirements into scalable system architecture, technology roadmaps, and platform features.
- Drive architecture tradeoff analysis across performance, power, cost, scalability, and deployment requirements to influence product direction.
One or More of the Following Domains:
AI / NPU Architecture
- Analyze and optimize AI workloads including LLMs, Transformers, computer vision, multimodal AI, and recommendation systems.
- Drive HW/SW co-design across architecture, compiler, runtime, driver, and framework layers.
- Lead performance analysis and optimization across compute, memory, and communication subsystems.
GPU & Graphics Architecture
- Analyze graphics, rendering, compute, and AI workloads to optimize performance, efficiency, and scalability.
- Drive architecture of GPU compute pipelines, graphics pipelines, memory systems, scheduling, and data movement.
- Collaborate with graphics software, driver, runtime, and application teams to optimize workload execution and user experience.
System Interconnect & Data Center Architecture
- Architect high-performance data movement across compute, memory, storage, and networking subsystems.
- Define scale-up and scale-out architectures using PCIe, CXL, Ethernet, UALink, or similar communication fabrics.
- Drive architecture of cache-coherent fabrics, memory hierarchies, chiplet communication, and distributed AI systems.
- Lead system-level architecture decisions for scalability, performance-per-watt, latency, and overall system efficiency.
Required Qualifications
- BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or related field.
- 10+ years of experience in AI accelerator, GPU, high-performance compute, system architecture, or related disciplines.
- Deep expertise in one or more of the following areas:
- AI accelerator / NPU architecture
- GPU architecture, graphics pipeline, and compute architecture
- High-performance interconnects and communication fabrics
- Data center system architecture
- Memory hierarchy and bandwidth optimization
- AI workload performance analysis and modeling
- Strong HW/SW co-design background with a solid understanding of how AI software stacks, compilers, runtimes, and drivers utilize underlying hardware resources.
- Demonstrated ability to drive architecture decisions across hardware, software, memory, and communication subsystems.
Language Requirements
- Fluent in both Mandarin Chinese and English.
- Able to lead technical discussions and collaborate effectively across global engineering teams.
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 8+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 7+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
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