Staff Engineer – STA Methodology/CAD
Qualcomm · Bangalore, India · 16d ago
Company:
Qualcomm India Private LimitedJob Area:
Engineering Group, Engineering Group > Hardware EngineeringGeneral Summary:
As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives digital transformation to help create a smarter, connected future for all. As a Qualcomm Hardware Engineer, you will plan, design, optimize, verify, and test electronic systems, bring-up yield, circuits, mechanical systems, Digital/Analog/RF/optical systems, equipment and packaging, test systems, FPGA, and/or DSP systems that launch cutting-edge, world class products. Qualcomm Hardware Engineers collaborate with cross-functional teams to develop solutions and meet performance requirements.
Minimum Qualifications:
• Bachelor's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 4+ years of Hardware Engineering or related work experience.OR
Master's degree in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 3+ years of Hardware Engineering or related work experience.
OR
PhD in Computer Science, Electrical/Electronics Engineering, Engineering, or related field and 2+ years of Hardware Engineering or related work experience.
Job Overview
We are seeking a highly motivated Staff Engineer – STA Methodology to drive the development, deployment, and enhancement of next-generation Static Timing Analysis (STA) methodologies for complex SoCs. The ideal candidate will have strong expertise in timing signoff, constraint methodologies, automation, and timing closure flows across advanced technology nodes.
Key Responsibilities:
Define, develop, and improve STA methodologies for block, subsystem, and full-chip designs.
Drive timing signoff flows including MMMC analysis, constraint validation, ECO methodologies, and correlation strategies.
Develop automation and infrastructure using Tcl/Python/Perl to improve timing analysis efficiency and turnaround time.
Own methodology development for timing closure, reporting, constraint management, and signoff quality metrics.
Collaborate closely with RTL, Synthesis, Physical Design, DFT, and CAD teams to enable robust timing convergence.
Drive adoption of advanced timing techniques including SOCV/AOCV, hierarchical STA, and signoff optimization flows.
Debug complex timing issues and provide scalable solutions across multiple projects.
Evaluate and deploy new EDA tool capabilities and AI-driven timing closure methodologies.
Mentor junior engineers and provide technical leadership across STA methodology initiatives.
Minimum Qualifications:
Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or related field.
7+ years of experience in STA, Timing Signoff, Timing Methodology, or CAD/EDA methodology development.
Strong understanding of:
Static Timing Analysis (STA)
MMMC timing signoff
Timing constraints (SDC)
Setup/Hold closure methodologies
SOCV/AOCV derates
ECO and timing convergence techniques
Expertise with Synopsys PrimeTime or Cadence Tempus.
Strong scripting skills in Tcl and Python.
Preferred Qualifications:
Experience with advanced technology nodes (7nm and below).
Experience developing timing automation frameworks, dashboards, and reporting infrastructure.
Knowledge of Synthesis, Physical Design, DFT, and power-aware timing analysis.
Exposure to AI/ML-driven timing optimization and methodology development.
Proven track record of driving methodology improvements adopted across multiple programs.
Strong communication, collaboration, and technical leadership skills.
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