DDR PHY System Design Engineer (San Diego, US)
Qualcomm · San Diego, United States · 10d ago
Company:
Qualcomm Technologies, Inc.Job Area:
Engineering Group, Engineering Group > ASICS EngineeringGeneral Summary:
QCT mixed-signal IP design team is looking for skilled system architect to help design high-speed, high-performance, and low-power DDR Phys for Qualcomm’s products targeted for 5G, AI/ML, compute, and automotive applications. This role is part of the DDR PHY design team. You’ll help with system design, building, and testing—starting from early ideas all the way to final chip production and validation.
Responsibilities:
- Analysis and ownership of DDR PHY system and architecture
- Development of system timing budgets, both on-die and off-chip.
- Lead and deliver best-in-class solutions for product needs
Required for this Role:
- 5-10 years in DDR PHY system design/architecture
- Strong knowledge in JEDEC DDR standards (LPDDR/PCDDR/HBM, etc.) and implication to DDR PHY system design/architecture
- Strong knowledge of link-budgets and trainings
- Strong communication skills; proven ability to collaborate across global teams
Preferred Qualifications:
- Knowledge of signal integrity and power delivery for server products
- Knowledge of latest process technology nodes and mixed-signal designs
- Solid understanding of design-for-yield and production challenges in high-speed links
- Unix/Perl/TCL scripting (must be comfortable with writing scripts)
Keywords
- DDR, DRAM, PHY, high-speed interface, signal integrity, power integrity.
Educational Requirements
- Required: Bachelor's, Electrical Engineering
- Preferred: Master's, Electrical Engineering
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.OR
Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
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Pay range and Other Compensation & Benefits:
$145,600.00 - $218,400.00The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.
If you would like more information about this role, please contact Qualcomm Careers.