DDR PHY Senior Lead Digital Design Engineer

Company:

Qualcomm India Private Limited

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

As a leading technology innovator, Qualcomm pushes the boundaries of what's possible to enable next-generation experiences and drives communication and data processing transformation to help create a smarter, connected future for all.  As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional groups to determine product execution path.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 1+ year of ASIC design, verification, validation, integration, or related work experience.

Role Overview

We are seeking a motivated and technically strong DDR PHY Digital Design Engineer to join our team working on next-generation memory interface IPs. The candidate will be responsible for the architecture, RTL implementation, verification support, synthesis, low-power design, DFT, and silicon bring-up of high-performance DDR PHY solutions used in leading-edge SoC products.

Responsibilities

• Design and develop digital components of high-performance DDR PHY for LPDDR/DDR memory interfaces.
• Participate in micro-architecture definition, RTL coding, integration, and debug of complex digital IPs.
• Drive RTL quality and signoff through lint, clock-domain crossing (CDC), reset-domain crossing (RDC), low-power, and design rule checks.
• Collaborate with the functional verification team to develop verification plans, review coverage closure, and debug design issues.
• Develop synthesis and timing constraints, analyze timing reports, and deliver high-quality netlists for physical design implementation.
• Create and maintain UPF-based low-power intent and perform equivalence checking, and low-power signoff.
• Implement and validate Design-for-Test (DFT) features, support scan insertion, ATPG generation, and optimize stuck-at and transition fault coverage.
• Work closely with physical design, STA, DFT, verification, and SoC integration teams to achieve project milestones and quality targets.
• Support pre-silicon and post-silicon bring-up, characterization, debug, and issue resolution across multiple product programs.
• Contribute to methodology improvements, automation, and design flow enhancements to improve engineering productivity and quality.

Required Qualifications

• B.Tech/M.Tech in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related discipline.
• 5+ years of experience in digital design and front-end implementation of complex ASIC/SoC/IP designs.
• Strong understanding of digital design fundamentals, RTL development using Verilog/SystemVerilog, and micro-architecture concepts.
• Hands-on experience with front-end design flows, including:
  • Lint
  • CDC/RDC
  • Low-power verification
  • Synthesis
  • Static Timing Analysis (STA)
  • Design-for-Test (DFT)
• Familiarity with industry-standard EDA tools used for RTL design, verification, synthesis, and timing closure.
• Strong debugging and problem-solving skills.
• Excellent teamwork, communication, and collaboration skills with global engineering teams.

Preferred Qualifications

• Experience in DDR/LPDDR PHY, high-speed interface, or mixed-signal IP development.
• Knowledge of UPF, power-aware design methodologies, and low-power architecture techniques.
• Familiarity with scan insertion, ATPG, and silicon debug activities.
• Exposure to post-silicon bring-up, validation, and characterization.
• Experience working across multi-functional teams, including verification, physical design, DFT, firmware, and system engineering.

What You'll Work On

• LPDDR5/LPDDR6 and future-generation memory PHY solutions.
• High-performance, low-power digital architectures for mobile, compute, XR, automotive, and AI platforms.
• State-of-the-art design methodologies spanning RTL design through silicon validation.

Applicants: Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail disability-accomodations@qualcomm.com or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

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